1. Field of the Invention
The present invention relates generally to a memory device. More specifically, the present invention relates to a translation lookaside buffer having a unified array access for two logically different arrays.
2. Description of the Relevant Art
Most modern computers use a virtual addressing scheme which allows the computer to access an address space that is larger than the computer's internal memory. In such a scheme, a virtual address must be translated to physical address before the memory can be accessed. Unfortunately, each translation process ordinarily requires multiple accesses to page and segment tables in the computer's memory, which significantly degrades the computer's performance.
To overcome this problem, a translation lookaside buffer (TLB) is often used to maintain the most recently used virtual address and corresponding physical address. Each TLB entry ordinarily contains a virtual address, a physical address mapped to the virtual address, and typically, special information bits indicative of size, writeability, error, etc. Before translating an input virtual address in the conventional manner, the TLB is searched to see if a physical address mapping for the input virtual address is present. If a physical address mapping is present in the TLB, the physical address may be obtained directly from the TLB and the conventional time wasting translation process is avoided.
FIG. 1 is a block diagram of the conventional TLB 10 which stores a set of virtual address/physical address translations. TLB 10 includes a content addressable memory (CAM) array 12 of CAM cells for storing virtual addresses, a first random access memory (RAM) array 14 of RAM1 cells for storing a plurality of special bits used to qualify the virtual to physical address translation, and a second RAM array 16 of RAM2 cells for storing physical addresses corresponding to virtual addresses stored in CAM array 12.
TLB 10 further includes a plurality of CAM write drivers 20, first RAM write drivers 22, and second RAM write drivers 24. Each of the write drivers 20-24 includes a pair of differential inputs, a control input, and a pair of differential outputs.
Each CAM write driver 20 has a pair of differential outputs coupled respectively to a pair of differential bit lines 30 and 32 within CAM array 12. The differential outputs of first RAM write drivers 22 are coupled respectively to differential bit lines 34 and 36 in first RAM array 14. Differential outputs of second RAM write drivers 24 are coupled respectively to differential bit lines 38 and 40 within second RAM array 16.
The control input of each CAM and first RAM write driver, 20 and 22, respectively, is coupled to a CAM/RAM1 write enable signal line 44. Similarly, each control input of second RAM write driver 24 is coupled to RAM2 write enable signal line 46. In general, the write drivers 20-24 write data to their corresponding storage cells in response to receiving a write enable signal. More particularly, CAM write drivers 20 write virtual address signals in the CAM cells via bit lines 30 and 32 when write drivers 20 receive the CAM/RAM1 write enable signal. First RAM write driver 22 write special bit signals to the RAM1 cells via bit lines 34 and 36 when write drivers 22 receive the CAM/RAM1 write enable signal. Second RAM write drivers 24 write physical address signals to RAM2 cells via differential bit lines 38 and 40 when write drivers 24 receive the RAM2 write enable signal.
TLB further includes CAM read sense amplifiers 50, first RAM read sense amplifiers 52, and second RAM read sense amplifiers 54. Each read sense amplifier has a pair of differential inputs, a control signal input, and a pair of differential outputs.
Each pair of differential inputs to CAM read sense amplifier 50 is coupled to a pair of differential bit lines 30 and 32 within CAM array 12. Each pair of differential inputs to first RAM read sense amplifier 52 is coupled to a pair differential bit lines 34 and 36 within first RAM array 14. Each pair of differential inputs of second RAM read sense amplifier 54 is coupled to a pair of differential bit lines 38 and 40 within second RAM array 16.
Each control input of CAM and first RAM read sense amplifiers 50 and 52, respectively, is coupled to a CAM/RAM1 read enable signal line 58. Each control input of second RAM read sense amplifier 54 is coupled to a RAM2 read enable signal line 60.
In general, each read sense amplifier generates a differential output signal as a function of a differential input signal and in response to receiving a read enable signal. Thus, CAM read sense amplifiers 50 output virtual address signals stored in the CAM cells in response to receiving the CAM/RAM1 read enable signal. First RAM read sense amplifiers 52 output special bit signals stored in the RAM2 cells in response to receiving the CAM/RAM1 read enable signal. Second RAM read sense amplifiers 54 outputs physical address signals stored in RAM2 cells in response to receiving the RAM2 read enable signal.
TLB 10 further includes a plurality of CAM/RAM1 word line drivers 64, and a plurality of RAM2 word line drivers 66. Each CAM/RAM1 word line driver 64 has an output coupled to a row or line of CAM and RAM1 cells within the CAM array 12 and first RAM array 14, respectively, via word line 68. Each RAM2 word line driver 66 is coupled to a row or line of RAM2 cells in second RAM array 16 via word line 70. Each CAM/RAM1 word line driver 64 generates a word line signal which activates a row of CAM and RAM1 cells. Word line driver 64 generates the word line signal in response to receiving a line address signal from a word line decoder (not shown). Likewise, each RAM2 word line driver 66 generates a word line signal which activates a row of RAM2 cell in response to RAM2 word line driver 66 receiving a line address signal from the word line decoder.
TLB 10 also includes a plurality of match sense amplifiers 74, each of which is coupled to a line of CAM cells within CAM array 12 via a match line 76. In a translation operation, one of the match sense amplifiers 74 sense when a virtual address inputted to CAM array 12 matches a virtual address stored within a line of CAM cells therein. As is to be noted within FIG. 1, each match sense amplifier 74 is coupled to one of the CAM/RAM1 word line drivers 64 and RAM2 word line drivers 66. When match sense amplifier 74 senses a match signal on match line 76 indicating that an input virtual address matches the contents of a row of CAM cells, match sense amplifier 74 outputs a signal to both CAM/RAM1 word line driver 64 and RAM to word line driver 66. Upon receipt of the signal from match sense amplifier 74, CAM/RAM1 word line driver 64 outputs a word line signal to its respective line of CAM and RAM1 cells. Similarly, when match sense amplifier 74 generates its signal, RAM2 word line driver 66 outputs a word line signal to its line of RAM2 cells.
CAM array 12 includes a plurality of CAM cells 80 arranged in x columns and n rows. Each row of CAM cells 80 stores a single x bit virtual address and, as noted above, is coupled to one of the CAM/RAM1 word lines 68. Each column of CAM cells 80 is coupled to a pair of CAM differential bit lines 30, 32, and a pair of CAM differential virtual address lines 82, 84. Each row of CAM cells 80, as noted above, is connected to one of the match lines 76. In an address translation, a virtual address is input to differential CAM virtual address bit lines 82 and 84. Thereafter, internal circuitry within CAM cells 80 compares the input virtual address with the CAM cell contents. If a row of CAM cells 80 stores an address which equates to the input virtual address, a match signal is provided on the corresponding match line 76. If the row of CAM cells 80 does not store the address corresponding to the input virtual address, a miss signal is provided on the corresponding match line 76.
Generally, each match sense amplifier 74 includes precharging circuitry (not shown) which precharges the match lines before an address translation cycle. The precharging circuitry is defined by a transistor coupled between a supply voltage and match line 76. The gate of the transistor is configured to receive a precharge pulse signal.
When the transistor is activated by the precharge pulse signal the transistor conducts current to charge match line 76 to a voltage substaintially equal to the supply voltage. Once precharged, CAM array 12 is provided with an input virtual address. If the virtual address does not equate to the contents of a row of CAM cells, one or more of the CAM cells will operate to discharge the corresponding match line 76 to a voltage substantially equal to ground, thereby providing a missed signal on match line 76. If the row of CAM cells contains an address equal to the input virtual address, none of the CAM cells within the row will discharge match line 76. Thus, match line 76 should keep its precharged voltage, thereby indicating a match signal. Match sense amplifier 74, is timed to generate an output signal indicative of the voltage on match line 76 at a particular instant of time. It is to be noted that within the prior art, each CAM cell 80 in a row is connected to a corresponding match sense amplifier 74 via a single sense line 76.
First RAM array 14 includes a plurality of RAM1 cells 88 arranged in n rows and y columns. Each row of RAM1 cells 88 stores n special bits associated with a virtual address stored in the corresponding line of CAM cells 80. Each row of RAM1 cells 88 is coupled to one of the word lines 68, and thus one of the CAM/RAM1 word line drivers 64. Each column of RAM1 cells 88 is coupled to corresponding pair of differential first RAM bit lines 34 and 36.
Second RAM array 16 comprises a plurality of RAM2 cells 98 arranged in n rows and z columns. The RAM2 cells 98 are substantially similar to the RAM1 cells 88. Each row of RAM2 cells stores a single z bit physical address. Each row of RAM2 cells 98 is coupled to one of the RAM2 word line drivers 66 via word line 70. Each column of RAM2 cells 98 is coupled to a corresponding pair of differential RAM2 bit lines 38 and 40. When one of the match sense amplifiers 74 detects a match of an input virtual address, the match sense 74 amplifier issues a corresponding signal to its associated RAM2 word line driver 66 and CAM/RAM1 word line driver 64, which in turn generates a word line signal to the corresponding rows of RAM2 cells 98 and RAM1 cells 88. In response, the corresponding row of RAM2 cells 98 output their physical address contents to differential bit lines 38 and 40, and the corresponding row of RAM1 cells output their special bits to differential bit lines 34 and 36. Read sense amplifiers 54 and 52 receive the physical address and special bits at their differential inputs, and acting in response to RAM2 and CAM/RAM1 read enable signals, output the physical address and special bits, which are concatenated and used to access the computer's main memory (not shown). It is to be noted that in this operation, the corresponding row of CAM cells also output their contents to bit lines 30 and 32.
As noted above, TLB 10 stores the most recently used virtual address/physical address pairs. Often times, TLB 10 must be updated with new virtual address/physical address pairs. TLB 10 is provided with read and write access modes to accomplish content updating. In one write access mode, CAM and first RAM write drivers 20 and 22, respectively, charge differential bit lines 30-36 as a function of data signals received at their inputs, and in response to CAM/RAM1 write enable signal. Thereafter, one of the CAM/RAM1 word line drivers 64, operating in response to a received line decode signal, generates a word line signal received by a corresponding line of CAM cells 80 and RAM1 cells 88. In response, the line of activated CAM cells 80 and RAM cells 88 store the values on differential lines 30-36. In a read operation, one of the CAM/RAM1 word line drivers 64 again receives a line decode signal and generates a word line signal which activates a row of CAM cells 80 and RAM1 cells 88. In response, the activated CAM cells 80 and RAM1 cells 88 output their stored contents onto differential bit lines 30-36. CAM read sense amplifiers 50 and first RAM read sense amplifiers 52 detect the voltage values at their inputs, and in response to a CAM/RAM1 read enable signal on line 58, generate corresponding values at their outputs. Second RAM array 16 is accessed in a similar fashion. It is to be noted that CAM array 12 and first RAM array 14 are accessed concurrently, while second RAM array 16 can be accessed independently of CAM array 12 and first RAM array 14 access.
FIG. 2 shows a schematic diagram of adjacent CAM and RAM1 cells from FIG. 1. RAM1 cell 88 is generally known in the art as a "T6" cell and includes a latch defined by a pair of cross coupled inverters 100 connected between a pair of pass gates 102. Each pass gate 102 is coupled to the output of a CAM/RAM1 driver 64 via a word line 68. Pass gates 102 and intervening inverters 100 are coupled between differential bit lines 34 and 36. Pass gates 102 connect nodes 104 to differential bit lines 34 and 36 in response to CAM/RAM1 line driver 64 charging word line 68 to a high voltage during a read or write operation.
CAM cell 80 includes the T6 circuitry of RAM1 cell 88. Additionally, CAM cell 80 includes match circuitry 106 for comparing a differential virtual address signal provided on differential virtual address bit lines 82 and 84 with the contents of CAM cell 80. Match circuitry 106 includes four transistors 110-116, the first two of which are coupled in series between match line 76 and ground, the second two of which are likewise coupled in series between match line 76 and ground. Transistors 110 and 114 have their gates coupled to nodes 104(a) and 104(b), respectively. Transistors 112 and 116 have their gates coupled to virtual address bit lines 82 and 84. Generally, virtual address bit line 84 is provided with the compliment of the signal on virtual address bit line 82. In operation, match line 76, as noted above, is precharged to a high voltage. If the signal provided on virtual address lines 82 and 84, equal that stored within CAM cell 80, match circuitry 106 will not activate and discharge match sense line 76. In effect, CAM cell 80 creates a match signal by maintaining line 76 at its precharge voltage. On the other hand, if the signal on virtual address lines 82 and 84 do not match the contents stored within CAM cell 80, match circuitry 106 will activate and discharge word line 76 to ground, in effect creating a miss signal on line 76.
As noted above, match sense amplifier 74 has an input coupled to match word line 76, and an output coupled to a corresponding CAM/RAM1 word line driver 64 and RAM2 word line driver 66 (not shown in FIG. 2). When match sense amplifier 74 detects a match between inputted virtual address and the contents of CAM cells 80, match sense amplifier 74 directs the CAM/RAM1 word line driver 64 and RAM2 word line driver 66 to drive word line 68 and 70 to a high voltage which in turn activates all CAM, RAM1 and RAM2 cells coupled thereto. RAM1 cells 88 output their content which are ultimately concatenated with the contents provided by the RAM2 cells.
In a virtual to physical address translation, virtual signals are provided to virtual address lines 82 and 84. If a match occurs between the input virtual address and the contents of a row of CAM cells 80, match sense amplifier 74 directs the corresponding CAM/RAM1 word line driver 64 and RAM2 word line driver to drive word line 68 and 70 to a high voltage. In response, CAM and RAM1 cells 80 and 88 output their data to bit lines 30-36. To translate, only the RAM1 cell contents are needed. Outputting the contents of the CAM cells results in needless power consumption. Further, the virtual address is deasserting just when the CAM/RAM1 word line is activating transistors 102(a) and 102(b). At this instant, their may be noise coupling between the virtual address lines 82 and 84 and bit lines 30 and 32, respectively. This noise could potentially corrupt the data stored within the CAM cells. To avoid data corruption under this scenario, metal lines 120 are added.
In a RAM1 write operation, data to be stored within RAM1 cells 88 are provided on differential bit lines 34 and 36. Thereafter, CAM/RAM1 word line driver 64 operates to activate pass gates 102 thereby coupling nodes 104 to differential bit lines 34 and 36. Once coupled, nodes 104 assume the values of voltage on the differential bit lines 34 and 36. Unfortunately, the pass gates 102 in CAM cell 80 are also activated by CAM/RAM1 word line driver 64. As a result, nodes 104 in CAM cell 80 are coupled to differential bit lines 30 and 32 simultaneously with a write operation to RAM2 cells 88. This provides an opportunity for data stored within CAM cells 80 to be corrupted by signals present on virtual address bit lines 30 and 32. More particularly, as can be seen in FIG. 2, the virtual address lines 82 and 84 run parallel with and adjacent to the differential CAM bit lines 30 and 32. The close proximity of these lines creates a capacitive coupling between signals thereon. When pass gates 102 in CAM cell 80 are activated, data on lines 82 and 84 may inadvertently alter data stored within CAM cell 80. To prevent this unwanted condition, metal lines 120 are provided between the differential bit lines and the differential address lines within each CAM cell 80. The metal lines 120 act to decouple the differential bit lines from the differential address lines and prevent corruption of signals in CAM cell 80 during a write to RAM1 cells 88.
Unfortunately, the decoupling metal lines 120 add significant horizontal thickness to the overall width of the translation lookaside buffer 10. In modem integrated circuit design in which translation lookaside buffer may be employed, overall size of the translation lookaside buffer is a critical design feature. Namely, it is desirable to limit the physical area occupied by the translation lookaside buffer. The addition of the middle lines 120 can add nearly 20% to the overall horizontal width of the CAM array 12.